Digital/analog conversion device and display device having the same

ABSTRACT

A pulse number control circuit inputs, to a charge pump circuit, pulses of a number according to digital data constituted of weighted data bits. The charge pump circuit includes a pump capacitor connected between a first node to which the pulses are input and a second node, a switch element connected between the second node and an output node, and a bias circuit. According to a change of a voltage on the output node, the bias circuit changes a voltage on the second node with the same polarity.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a digital/analog conversiondevice converting digital data into an analog voltage as well as adisplay device indicating a gray level with the analog voltage generatedby the digital/analog conversion device.

[0003] 2. Description of the Background Art

[0004] A digital/analog conversion device which converts digital datainto analog signals is commonly used. Such a digital/analog conversiondevice is used, for example, for generating an analog voltage so as todisplay a gray level (this voltage is hereinafter referred to as“gray-level voltage”) on a display device having, for each pixel, such avoltage-driven light-emitting device as a liquid-crystal display deviceor a current-driven light-emitting device of self-light-emitting type.

[0005] The above-described display device can display a gray level bysetting the gray-level voltage to a level between the maximum brightness(white) and the minimum brightness (black) for each pixel. In otherwords, the gray-level voltage is set to one of 2^(n) levels (n is anatural number) according to n-bit digital data and transmitted to eachpixel.

[0006] One of generally known digital/analog conversion devices isconstituted of a plurality of ladder-connected resistance elements (seefor example “Exhaustive Guide to Analog IC with Illustrations” by YoshioShirato, Tokyo Denki University Press, Nov. 1986, pp. 258-260). Such aladder-type digital/analog conversion device, however, has a problemthat the consumption current increases due to a constantly flowing DCcurrent.

[0007] Then, a digital/analog conversion device is disclosed for examplein Japanese Patent Laying-Open No. 2002-111499 (hereinafter referred toas “conventional art”) that has a charge pump circuit used tocharge/discharge a capacitor element and thereby change an outputvoltage in a stepwise manner.

[0008] The digital/analog conversion device of the conventional art thatuses the charge pump circuit can reduce its power consumption since noconstant DC current is generated therein.

[0009] However, regarding the digital/analog conversion device of theconventional art that uses the charge pump circuit, a change in outputvoltage Vout between a pulse input and an immediately following pulseinput varies depending on the level of the output voltage Vout.Specifically, as the output voltage Vout is higher, the change in outputvoltage per pulse input gradually approaches saturation.

[0010] Therefore, in order to set the output voltage Vout in such amanner that the output voltage changes at regular intervals, it would benecessary to control the number of clocks to be input to the charge pumpcircuit according to the level of the output voltage Vout, possiblyresulting in a complicated circuit configuration. It is expected thatthis problem becomes noticeable when the digital/analog conversiondevice is employed for generating a gray-level voltage for a displaydevice.

SUMMARY OF THE INVENTION

[0011] An object of the present invention is to provide a digital/analogconversion device of low power consumption accomplished by acharge-pump-circuit operation that is configured to allow an outputanalog voltage to change at regular intervals according to the number ofinput pulses, and to provide a display device having such adigital/analog conversion device.

[0012] A digital/analog conversion device according to the presentinvention is a digital/analog conversion device outputting an analogvoltage according to digital data of a plurality of weighted bits, andincludes, a pulse number control circuit supplying, to a first node,pulses of a number according to the digital data, the pulses including afirst transition edge changing from an initial level to a predeterminedlevel and a second transition edge returning from the predeterminedlevel to the initial level, and a charge pump circuit changing, in astepwise manner, each time one of the pulses is supplied to the firstnode, a voltage on an output node having an output capacitor connectedthereto. The charge pump circuit includes a pump capacitor connectedbetween a second node and the first node, a switch element connectedbetween the second node and the output node to be turned on at a timingat which the first transition edge of each of the pulses is transmittedto the first node and turned off at a timing at which the secondtransition edge thereof is transmitted to the first node, and a biascircuit changing, according to the change of the voltage on the outputnode, a voltage on the second node with the same polarity as that of thechange of the voltage on the output node.

[0013] A display device according to the present invention is a displaydevice displaying a gray level based on display data constituted ofweighted n bits where n is an integer of at least two, and includes, aplurality of pixel circuits each indicating a brightness according to asupplied voltage, a selection line for selecting the pixel circuits, adata line connected to the pixel circuits, and a gray-level voltagegeneration circuit for supplying to the data line a gray-level voltagethat is an analog voltage according to the display data. The gray-levelvoltage generation circuit includes a pulse number control circuitsupplying, to a first node, pulses of a number according to the displaydata, the pulses including a first transition edge changing from aninitial level to a predetermined level and a second transition edgereturning from the predetermined level to the initial level, and acharge pump circuit changing, in a stepwise manner, each time one of thepulses is supplied to the first node, a voltage on an output nodeconnected to the data line.

[0014] According to the present invention, a display device with anotherconfiguration is a display device displaying a gray level based ondisplay data constituted of weighted n bits where n is an integer of atleast two, and includes, a plurality of pixel circuits each having adisplay element indicating a brightness according to a supplied voltageto the pixel circuit, a data line connected to the pixel circuits, and agray-level voltage generation circuit for supplying to the data line agray-level voltage that is an analog voltage according to the displaydata. The gray-level voltage generation circuit includes a pulse controlunit successively receiving pulses including a first transition edgechanging from an initial level to a predetermined level and a secondtransition edge returning from the predetermined level to the initiallevel, and outputting the pulses or inverted pulses that are invertedversions of the pulses according to a specified bit among the n bits, apulse number control circuit receiving the pulses or the inverted pulsesthat are output from the pulse control unit, and transmitting, to afirst node, the pulses or the inverted pulses of a number according tothe display data, a first charge pump circuit increasing, in a stepwisemanner, in response to each of the pulses transmitted to the first node,a voltage on a first output node connected to the data line, and asecond charge pump circuit decreasing, in a stepwise manner, in responseto each of the inverted pulses transmitted to the first node, a voltageon a second output node connected to the data line.

[0015] A chief advantage of the present invention is therefore that thecharge pump circuit of a relatively simple configuration of thedigital/analog conversion device can be used to generate an analogvoltage with low power consumption that changes at regular intervals ina stepwise manner according to digital data of a plurality of weightedbits.

[0016] Further, the display device of the present invention can use thecharge pump circuit to generate an analog voltage for gray-level displaywith low power consumption that changes in a stepwise manner accordingto display data of a plurality of weighted bits.

[0017] Moreover, the display device can use the upcharge pump circuitand the downcharge pump circuit that are selectively operated togenerate an analog voltage for gray-level display. Then, as comparedwith such a configuration in which only one of the upcharge anddowncharge pump circuits is used, the gray-level voltage can morespeedily be generated.

[0018] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a circuit diagram showing a configuration of adigital/analog conversion device according to a first embodiment of thepresent invention.

[0020]FIG. 2 is a circuit diagram showing a configuration of a switchcontrol circuit shown in FIG. 1.

[0021]FIG. 3 is an operational waveform chart illustrating an operationof a pulse number control circuit shown in FIG. 1.

[0022]FIG. 4 illustrates an operation of the digital/analog conversiondevice shown in FIG. 1.

[0023]FIG. 5 is a circuit diagram showing an internal state of a chargepump circuit at time t6 and therearound in FIG. 4.

[0024]FIG. 6 is a circuit diagram showing a configuration of adigital/analog conversion device according to a modification of thefirst embodiment.

[0025]FIGS. 7 and 8 are circuit diagrams showing respectiveconfigurations of digital/analog conversion devices according to asecond embodiment and a modification thereof of the present invention.

[0026]FIGS. 9 and 10 are circuit diagrams showing respectiveconfigurations of digital/analog conversion devices according to a thirdembodiment and a modification thereof of the present invention.

[0027]FIGS. 11-15 are circuit diagrams showing respective configurationsof digital/analog conversion devices according to first to fifthexemplary configurations of a fourth embodiment.

[0028]FIG. 16 is a circuit diagram showing a configuration of adigital/analog conversion device according to a fifth embodiment.

[0029]FIG. 17 is a block diagram showing an entire configuration of adisplay device according to a sixth embodiment.

[0030]FIG. 18 is a circuit diagram showing an exemplary configuration ofa pixel circuit including an EL element.

[0031]FIG. 19 is a cross-sectional view illustrating a parasiticcapacitance of a data line that is an output capacitor of a charge pumpcircuit in a liquid-crystal display device.

[0032]FIG. 20 conceptually shows how a pump capacitor of the sixthembodiment is formed.

[0033]FIGS. 21 and 22 show first and second exemplary configurationsrespectively of pump capacitors according to the sixth embodiment.

[0034]FIG. 23 is a block diagram showing a first exemplary configurationof a gray-level voltage generation circuit according to a seventhembodiment.

[0035]FIG. 24 is a circuit diagram showing a configuration of a pulsenumber control circuit shown in FIG. 23.

[0036]FIG. 25 is a block diagram showing an exemplary configuration of agray-level voltage generation circuit according to a modification of theseventh embodiment.

[0037]FIG. 26 is a circuit diagram showing a configuration of a pulsenumber control circuit shown in FIG. 25.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] Embodiments of the present invention are hereinafter described indetail with reference to the drawings. It is noted that like componentsare denoted by like reference characters in the following description.

[0039] First Embodiment

[0040] Referring to FIG. 1, a digital/analog conversion device 10 of afirst embodiment includes a pulse number control circuit 20, a chargepump circuit 30, and precharge switches 51-53 serving as a prechargecircuit. Digital/analog conversion device 10 generates, according toinput digital data, an analog voltage VNo on an output node No to whichan output capacitor 5 is connected.

[0041] In this embodiment of the present invention, it is supposed thatthe input digital data has 4 bits, namely the input digital data isconstituted of weighted data bits D0-D3 among which data bit D0 is theleast significant bit (LSB) and data bit D3 is the most significant bit(MSB), and a description of this embodiment will be given accordingly.

[0042] As clearly seen from the following description, the number ofbits of input digital data is not limited to the above-described one andthe digital/analog conversion device of the present invention may beconfigured to be adapted to digital data of an arbitrary number of bits.

[0043] Pulse number control circuit 20 includes switch elements 22-25constituting a switch circuit and a switch control circuit 27. Switchelements 22-25 are connected in parallel between a node 21 to whichpulses CP are successively supplied and a node N1.

[0044] Switch control circuit 27 generates, according to data bitsD0-D3, control signals D0C-D3C respectively controlling respective ONperiods of switch elements 22-25.

[0045] Switch 22 is turned on when control signal D0C has a logical highlevel (hereinafter simply referred to as “H level”) and turned off whencontrol signal D0C has a logical low level (hereinafter simply referredto as “L level”). Similarly, switch elements 23-25 are turned on/off inresponse to respective control signals D1C-D3C. Switch elements 22-25 inthe ON state each transmit pulses CP from node 21 to node N1.

[0046] Charge pump circuit 30 includes a pump capacitor 32 connectedbetween nodes N1 and N2, a switch element 34 connected between node N2and output node No, and a bias circuit 40 provided between apower-supply node NR to which a predetermined voltage VR is applied andnode N2.

[0047] Switch element 34 is, for example, constituted of a p-typetransistor, an n-type transistor or a combination of the p- and n-typetransistors connected in parallel to be turned on/off in response to acontrol signal φ1. Bias circuit 40 has an n-type transistor 41 connectedbetween power-supply node NR and node N2. The gate of n-type transistor41 is connected to output node No.

[0048] Precharge switches 51, 52 and 53 are connected respectivelybetween nodes N1, N2 and output node No and a power-supply node NL towhich a predetermined low voltage VDL is applied. Precharge switches51-53 are each turned on/off in response to a precharge signal φp. Here,it is supposed that low voltage VDL corresponds to the minimum level ina range over which output voltage VNo is controlled that is generatedaccording to input digital data. Predetermined voltage VR is a voltagethat is at least higher than low voltage VDL.

[0049] Output node No has output capacitor 5 connected between it and apredetermined voltage Vss (typically ground voltage). It is hereinaftersupposed that pump capacitor 32 has a capacitance of Cp and outputcapacitor 5 has a capacitance of Co.

[0050] An operation of pulse number control circuit 20 is now described.

[0051]FIG. 2 is a circuit diagram showing a configuration of switchcontrol circuit 27 shown in FIG. 1.

[0052] Referring to FIG. 2, switch control circuit 27 has logic gates 28a-28 d generating control signals D0C-D3C respectively. Logic gate 28 agenerates control signal D0C as a result of an AND logical operation ona control signal C0 and data bit D0, and logic gate 28 b generatescontrol signal D1C as a result of an AND logical operation on a controlsignal C1 and data bit D1. Similarly, logic gate 28 c generates controlsignal D2C as a result of an AND logical operation on a control signalC2 and data bit D2, and logic gate 28 d generates control signal D3C asa result of an AND logical operation on a control signal C3 and data bitD3.

[0053]FIG. 3 is an operational waveform chart illustrating the operationof pulse number control circuit 20.

[0054] Referring to FIG. 3, to node 21 shown in FIG. 1, pulses CP aresuccessively provided including a transition edge from L level to Hlevel (rising edge) and a transition edge from H level to L level(falling edge). As an example, one period T includes (2^(n)−1) pulses CP(15 pulses in FIG. 3) according to the number of bits “n” of a digitalsignal.

[0055] In each period T, control signal C0 corresponding to data bit D0of the least significant digit is set to H level during the period oftime ta-tb containing one pulse CP and is set to L level during theremaining period of time. Similarly, control signal C1 is set to H levelduring the period of time tb-tc such that the H level period containstwo pulses CP and is set to L level during the remaining period of time.Control signal C2 is set to H level during the period of time tc-td suchthat the H level period contains four pulses CP. Further, control signalC3 corresponding to data bit D3 of the most significant digit is set toH level during the period of time td-te such that the H level periodcontains eight pulses CP.

[0056] Accordingly, in one period T, at the timing at which each pulseCP is transmitted to node 21, one of control signals C0-C3 is set to Hlevel while remaining signals are set to L level. Further, the ratiobetween respective H level periods of control signals C0-C3 isdetermined by raising 2 to the power of respective bit weights, namely,the ratio is set to 1:2:4:8.

[0057] Thus, in each of the time periods ta-tb, tb-tc, tc-td and td-te,pulse number control circuit 20 shown in FIG. 1 does not transmit pulseCP to node N1 when a corresponding one of data bits D0-D3 is “0” whiletransmits, if a corresponding one of data bits D0-D3 is “1”, thecorresponding number of pulses CP according to the H level period ofcontrol signals C0-C3.

[0058] Thus, for one period T, the number of pulses CP transmitted bypulse number control circuit 20 from node 21 to node N1 is set to“D0+2·D1+4·D2+8·D3 (D0, D1, D2, D3=“0” or “1”)”.

[0059] An operation of digital/analog conversion device 10 is nowdescribed in connection with FIG. 4.

[0060] Referring to FIG. 4, before output voltage VNo is output,precharge signal φp is set to H level for a predetermined period of time(t0-t1) so that nodes N1 and N2 and output node No are each prechargedto low voltage VDL. Accordingly, a voltage VN1 on node N1, a voltage VN2on node N2 and output voltage VNo on output node No are set to have arelation VN1=VN2=VNo=VDL. It is hereinafter supposed that the voltage oneach node or the like is represented as a voltage with respect to lowvoltage VDL (i.e., VDL=0 (V)).

[0061] In response to transmission of the first pulse CP, voltage VN1 onnode N1 increases from low voltage VDL by V1 in the period of timet3-t5. Control signal φ1 is set to H level in the period of time t2-t4so as to allow switch element 34 to be turned on at the timing at whichthe rising edge of pulse CP is transmitted to node N1 (time t3) andturned off at the timing at which the falling edge thereof istransmitted thereto (time t5). Switch element 34 is turned on in the Hlevel period of control signal φ1 and turned off in the L level periodthereof.

[0062] At time t3, the amount V1 by which voltage VN1 increases istransmitted by capacitive coupling through pump capacitor 32 to node N2and output node No connected by switch element 34. Accordingly, voltagesVN2 and VNo each increase by V2. Here, the amount of the voltageincrease V2 is represented by Equation (1):

V 2=V 1·Cp/(Cp+Co)  (1).

[0063] At time t4, control signal φ1 is set to L level so that switchelement 34 is turned off. Further, at time t5, in response totransmission of the falling edge of pulse CP to node N1, voltage VN1decreases by V1. Accordingly, voltage VN2 decreases by V1 because of thecapacitive coupling. However, since switch element 34 is in OFF state,output voltage VNo is kept at V2.

[0064] In response to the decrease of voltage VN2, n-type transistor 41constituting bias circuit 40 is turned on. Here, by settingpredetermined voltage VR in such a manner that n-type transistor 41operates in a saturation region, n-type transistor 41 operates in asource-follower mode. Thus, since the gate voltage (i.e., output voltageVNo) of n-type transistor 41 is V2, voltage VN2 on node N2 returns to“V2−VTN”. VTN is the threshold voltage of n-type transistor 41. Thus,according to a change of voltage VNo on output node No, bias circuit 40changes voltage VN2 on node N2 with the same polarity (one of increaseand decrease) as that with which the output voltage changes.

[0065] In the period of time t7-t9, the following pulse CP istransmitted to node N1. Control signal φ1 is set again to H level in theperiod of time t6-t8 including a rising edge (time t7) and including nofalling edge (time t9).

[0066] Before time t6, the voltage on node N2, i.e., VN2 is equal toV2−VTN and output voltage VNo is equal to V2, so that an AC currentflows from output node No having a relatively higher potential to nodeN2 in response to the turning-on of switch element 34 at time t6. Then,voltage VN2 increases by VA while output voltage VNo decreases by VB sothat the voltages become equal to each other, i.e., VN2=VNo. The amountof change in voltage, VA and VB, are determined according tocapacitances Cp and Co.

[0067]FIG. 5 is a circuit diagram showing an internal state of thecharge pump circuit at time t6 and therearound shown in FIG. 4,specifically, showing respective states of node N2 and output node No.

[0068] Referring to FIG. 5, switch element 34 is turned on at time t6 inresponse to control signal φ1 so that node N2 and output node No reachthe same voltage VX. Before and after the turning-on of switch element34, no charge is supplied/received to/from other circuit elements.Therefore, the charge conservation law is established and voltage VX isrepresented by Equation (2):

Cp·(V 2−VTN)+Co·V 2=(Cp+Co)·VX  (2).

[0069] From Equation (2), voltage VX is represented by Equation (3):$\begin{matrix}{{VX} = {{\left( {{{Cp} \cdot {V2}} + {{Co} \cdot {V2}} - {{Cp} \cdot {VTN}}} \right)/\left( {{Cp} + {Co}} \right)}\quad = {{V2} - {{Cp} \cdot {{VTN}/{\left( {{Cp} + {Co}} \right).}}}}}} & (3)\end{matrix}$

[0070] Then, the amount of voltage decrease VB of output node No shownin FIG. 4 is represented by Equation (4):

VB=Cp·VTN/(Cp+Co)  (4).

[0071] In the period of time t7-t9, a similar charge pump operation isdone in response to transmission of the following pulse CP, so thatoutput voltage VNo when the second charge pump operation is finished isequal to 2·V2−VB. Further, in the period of time t11-t13, the thirdpulse CP is transmitted to node N1 and a similar charge pump operationis done accordingly. When the third charge pump operation is finished,output voltage VNo is equal to 3·V2−2·VB.

[0072] In this way, output voltage VNo is set, in response to the numberm (m is a natural number) of pulses CP transmitted by pulse numbercontrol circuit 20 to node N1, as shown by Equation (5):

VNo=m·V 2−(m−1)·VB  (5).

[0073] The amount of change in voltage ΔV on output node No per pulse CPis thus represented by ΔV=V2−VB and is a constant value regardless ofthe level of output voltage VNo.

[0074] As discussed above, digital/analog conversion device 10 of thefirst embodiment can provide output voltage VNo which is proportional tothe number of pulses transmitted to charge pump circuit 30 that isdetermined according to digital data. The digitaUanalog conversiondevice of low power consumption and of simple circuit configuration canthus provide an analog voltage that changes at regular intervals in astepwise manner.

[0075] Modification of the First Embodiment

[0076] Referring to FIG. 6, a digital/analog conversion device 11according to a modification of the first embodiment differs fromdigital/analog conversion device 10 of the first embodiment shown inFIG. 1 in that the former includes a pulse number control circuit 20#instead of pulse number control circuit 20. The circuit configurationexcept for this is similar to that of digital/analog conversion device10 of the first embodiment and the detailed description thereof is notrepeated here.

[0077] Pulse number control circuit 20# differs from pulse numbercontrol circuit 20 shown in FIG. 1 in that the former includes a switchcontrol circuit 27# instead of switch control circuit 27 andadditionally includes switch elements 22#-25# connected in series withrespective switch elements 22-25 between node 21 and node N1.

[0078] Switch control circuit 27# transmits control signals C0-C3 shownin FIG. 3 to switch elements 22-25 respectively and switch elements22-25 are turned on/off in response to respective control signals C0-C3.

[0079] Switch elements 22#-25# are turned on/off in response torespective levels of data bits D0-D3. Specifically, switch elements#22-#25 are each turned on when a corresponding one of data bits D0-D3is “1” and turned off when the corresponding data bit is “0”.

[0080] Like pulse number control circuit 20, pulse number controlcircuit 20# shown in FIG. 6 can be configured to transmit pulses CP of anumber according to data bits D0-D3 from node 21 to node N1 and inputthe pulses to charge pump circuit 30.

[0081] The digital/analog conversion device of low power consumption andsimple configuration can thus provide an analog voltage changing atregular intervals in a stepwise manner, similarly to that of the firstembodiment.

[0082] Second Embodiment

[0083] Output voltage VNo of the digital/analog conversion devices ofthe first embodiment and the modification thereof includes, as shown inEquation (4), capacitances Cp and Co and threshold voltage VTN. Inusual, capacitances Cp and Co have low temperature dependency and areusually canceled in Cp/(Cp+Co) of Equation (4). On the other hand,threshold voltage VTN has relatively high temperature dependency so thatoutput voltage VNo could vary according to an increase in operatingtemperature of the digital/analog conversion device. In a secondembodiment, a configuration for solving the above-discussed problem isdescribed.

[0084] Referring to FIG. 7, a digital/analog conversion device 12 of thesecond embodiment differs from digital/analog conversion device 10 shownin FIG. 1 in that the former includes a charge pump circuit 130 insteadof charge pump circuit 30. Charge pump circuit 130 differs from chargepump circuit 30 in that the former includes a bias circuit 140 insteadof bias circuit 40.

[0085] Bias circuit 140 includes, in addition to n-type transistor 41, acurrent-limiting element 42 and a p-type transistor 43. Current-limitingelement 42 and p-type transistor 43 are connected in series betweenpower supply nodes respectively receiving voltages different from eachother. Although FIG. 7 shows current-limiting element 42 and p-typetransistor 43 that are connected between power supply node NR and theground node, they may be connected between power supply nodes receivingother voltages on the condition that a predetermined operation asdiscussed below can be accomplished.

[0086] The gate of p-type transistor 43 is connected to output node Noand a node N3 corresponding to a connection node of current-limitingelement 42 and p-type transistor 43 is connected to the gate of n-typetransistor 41.

[0087] Digital/analog conversion device 12 has its configuration similarto that of digital/analog conversion device 10 shown in FIG. 1 exceptfor the above-described differences, and the detailed descriptionthereof is not repeated here.

[0088] Current-limiting element 42 is typically constituted of aresistor element. By setting the resistance value of the resistorelement to a value which is sufficiently higher. than an on-stateresistance value of p-type transistor 43, a voltage VN3 on node N3 canbe set as shown by Equation (6) below without substantially increasingpower consumption.

V 3=VNo+|VTP|  (6)

[0089] Here, |VTP| is the absolute value of the threshold voltage ofp-type transistor 43. Then, to the gate of n-type transistor 41, avoltage which is higher by |VTP| than output voltage VNo is input.Accordingly, the element (V2−VTN) in Equation (2) is replaced with(V2−VTN+|VTP|). Thus, for the digital/analog conversion device of thesecond embodiment, voltage VB in Equation (4) is represented by Equation(7):

VB=Cp·(VTN−|VTP|)/(Cp+Co)  (7).

[0090] The effect achieved by manufacturing n-type transistor 41 andp-type transistor 43 through similar manufacturing processes to belocated close to each other, i.e., so-called pairing effect, allowsrespective temperature coefficients of the absolute values of thresholdvoltages of n-type transistor 41 and p-type transistor 43 to besubstantially equal to each other. Then, the temperature dependencies inelement (VTN−|VTP|) of Equation (7) are cancelled.

[0091] Accordingly, the digital/analog conversion device of the secondembodiment can provide, in addition to the effect of the digital/analogconversion device of the first embodiment, the effect of reducing thetemperature dependency of the output voltage.

[0092] Modification of the Second Embodiment

[0093] Referring to FIG. 8, a digital/analog conversion device 13according to a modification of the second embodiment differs fromdigital/analog conversion device 12 shown in FIG. 7 in that the formerincludes a charge pump circuit 131 instead of charge pump circuit 130.Charge pump circuit 131 differs from charge pump circuit 130 in that theformer includes a bias circuit 141 instead of bias circuit 140.

[0094] Bias circuit 141 differs from bias circuit 140 in thatcurrent-limiting element 42 is constituted of a constant current source44. Constant current source 44 supplies a constant small current to nodeN3 and this small current flows via p-type transistor 43 to the groundnode. Then, the voltage on node N3 is set as done in FIG. 7.

[0095] In particular, use of constant current source 44 ascurrent-limiting element 42 can keep a constant relation between voltageVN3 on node N3 and output voltage VNo regardless of a voltage differencebetween node N3 and power supply node NR. In other words, indigital/analog conversion device 12 in FIG. 7 that includes bias circuit140, the amount of decrease in voltage of current-limiting element 42could vary depending on output voltage VNo so that the temperaturedependency of output voltage VNo is somewhat inferior to that ofdigital/analog conversion device 13 shown in FIG. 8.

[0096] Thus, the digital/analog conversion device of the modification ofthe second embodiment provides, in addition to the effect of thedigital/analog conversion device of the second embodiment, an effectthat the amount of stepwise change in output voltage VNo, namely ΔV, canaccurately be set by further reducing the temperature dependency.

[0097] Third Embodiment

[0098] Regarding the digital/analog conversion devices according to thesecond embodiment and the modification thereof, voltage VB which affectsoutput voltage VNo includes the element (VTN−|VTP|) as seen fromEquation (7).

[0099] Threshold voltages VTN and |VTP| each of the transistor couldvary depending on process variation in manufacturing. If the influenceof the variation causes the value determined by (VTN−|VTP|) to vary, thelevel of output voltage VNo could vary due to the variation of thetransistor characteristics (threshold voltages). With a configuration ofa third embodiment, the above-described problem is solved and therebyoutput voltage VNo is more accurately set, as described below.

[0100] Referring to FIG. 9, a digital/analog conversion device 14 of thethird embodiment differs from digital/analog conversion device 12 shownin FIG. 7 in that the former includes a charge pump circuit 132 insteadof charge pump circuit 130. Charge pump circuit 132 differs from chargepump circuit 130 in that the former includes a bias circuit 142 insteadof bias circuit 140.

[0101] Bias circuit 142 differs from bias circuit 140 in that the formerfurther includes a p-type transistor 45 connected between n-typetransistor 41 and node N2 and an n-type transistor 46 connected betweennode N3 and p-type transistor 43. P-type transistor 45 isdiode-connected and has its gate connected to node N2. Similarly, n-typetransistor 46 is diode-connected and has its gate connected to node N3.

[0102] The configuration of digital/analog conversion device 14 issimilar to that of digital/analog conversion device 12 shown in FIG. 7except for the above-described differences and the detailed descriptionthereof is not repeated here.

[0103] For bias circuit 142, voltage V3 on node N3 is represented byEquation (8):

V 3=VNo+VTN+|VTP|  (8).

[0104] In other words, a voltage greater than output voltage VNo byVTN+|VTP| is applied to the gate of n-type transistor 41. By connectingthe diode-connected p-type transistor 45, the element (V2−VTN) inEquation (2) is now (V2−VTN−|VTP|). Accordingly, the element (V2−VTN) inEquation (2) is replaced with V2 so that VB=0 can be established forEquation (4).

[0105] Thus, output voltage VNo of digital/analog conversion device 14according to the third embodiment is represented by Equation (9)depending only on V2 in Equation (1):

VNo=m·V 2  (9).

[0106] The digital/analog conversion device of the third embodimentaccordingly provides, in addition to the effect of the digital/analogconversion device of the first embodiment, an effect that output voltageVNo can more accurately be generated by eliminating the influence of themanufacturing-related variation of the threshold voltages of thetransistors. Moreover, since ΔV is easily ensured, the range of theoutput voltage can be expanded.

[0107] Modification of the Third Embodiment

[0108] Referring to FIG. 10, a digital/analog conversion device 15 of amodification of the third embodiment differs from digital/analogconversion device 14 shown in FIG. 9 in that the former includes acharge pump circuit 133 instead of charge pump circuit 132. Charge pumpcircuit 133 differs from charge pump circuit 132 in that the formerincludes a bias circuit 143 instead of bias circuit 142.

[0109] Bias circuit 143 differs from bias circuit 142 shown in FIG. 9 inthat the former has current-limiting element 42 constituted of constantcurrent source 44. Constant current source 44 is described above inconnection with FIG. 8, and thus the detailed description thereof is notrepeated here.

[0110] Since constant current source 44 is used as current-limitingelement 42, the digital/analog conversion device of the modification ofthe third embodiment can provide, in addition to the effect of thedigital/analog conversion device of the third embodiment, an effect thatoutput voltage VNo can accurately be set by further reducing thetemperature dependency.

[0111] Although digital/analog conversion devices 11-15 of the secondand third embodiments and respective modifications each include pulsenumber control circuit 20 shown in FIG. 1 and are accordingly described,the digital/analog conversion devices may use pulse number controlcircuit 20# shown in FIG. 6 instead of pulse number control circuit 20.

[0112] Fourth Embodiment

[0113] In a fourth embodiment, with regard to digital/analog conversiondevices of the first to third embodiments and respective modifications,descriptions are given each of a configuration of a digital/analogconversion device of the opposite polarity, namely, a digital/analogconversion device providing output voltage VNo decreasing in a stepwisemanner in response to input of each pulse CP.

[0114] Referring to FIG. 11, a digital/analog conversion device 10# of afirst exemplary configuration of the fourth embodiment has itsconfiguration corresponding to that of digital/analog conversion device10 shown in FIG. 1 and has the opposite polarity with respect to outputvoltage VNo.

[0115] Digital/analog conversion device 10# includes a pulse numbercontrol circuit 20 (or 20#), a charge pump circuit 30# and prechargeswitches 51-53. Charge pump circuit 30# includes a pump capacitor 32, aswitch element 34 and a bias circuit 40#.

[0116] Bias circuit 40# includes a p-type transistor 41# connectedbetween a power supply node NR# and a node N2. The gate of p-typetransistor 41# is connected to an output node No. Precharge switches51-53 are connected between a power supply node NH to which a highvoltage VDH is supplied and nodes N1 and N2 and output node Norespectively, and they are turned on/off in response to a prechargesignal φp.

[0117] The configuration and operation of pulse number control circuit20 or #20 are similar to those described in connection with the firstembodiment and its modification and the detailed description thereof isnot repeated here.

[0118] High voltage VDH corresponds to the highest level in a range overwhich output voltage VNo is controlled that is generated according toinput digital data. To a power supply node NR#, a predetermined voltageVR# which is at least lower than high voltage VDH is supplied.

[0119] Charge pump circuit 30# operates in a manner of the oppositepolarity to that represented by the operational waveform shown in FIG.4. Each time one pulse CP is transmitted to node N1, charge pump circuit30# decreases output voltage VNo in a stepwise manner by ΔV in responseto the falling edge of pulse CP.

[0120] Accordingly, digital/analog conversion device 10# of the fourthembodiment has a similar effect to that of the digital/analog conversiondevice 10 shown in FIG. 1 and can further generate an analog voltagechanging at regular intervals in a stepwise manner according to digitaldata.

[0121] Referring to FIG. 12, a digital/analog conversion device 12# of asecond exemplary configuration of the fourth embodiment differs fromdigital/analog conversion device 10# shown in FIG. 11 in that the formerincludes a charge pump circuit 130# instead of charge pump circuit 30#.Charge pump circuit 130# differs from charge pump circuit 30# in thatthe former includes a bias circuit 140# instead of bias circuit 40#.

[0122] Bias circuit 140# includes, in addition to p-type transistor 41#,a current-limiting element 42 and an n-type transistor 43#.Current-limiting element 42 and n-type transistor 43# are connected inseries between power supply nodes receiving respective voltagesdifferent from each other. Although current-limiting element 42 andn-type transistor 43# in FIG. 12 are connected between power supply nodeNR# and power supply node NH, they may be connected to power supplynodes to which other voltages are supplied.

[0123] The configuration of digital/analog conversion device 12# issimilar to that of digital/analog conversion device 10# shown in FIG. 11except for the above described differences and the detailed descriptionthereof is not repeated here.

[0124] In other words, digital/analog conversion device 12# isconfigured correspondingly to digital/analog conversion device 12 shownin FIG. 7 and has the opposite polarity with respect to output voltageVNo. Thus, digital/analog conversion device 12# of the fourth embodimenthas a similar effect to that of digital/analog conversion device 12 ofthe second embodiment and can generate an analog voltage that changes atregular intervals in a stepwise manner according to digital data.

[0125] Referring to FIG. 13, a digital/analog conversion device 13# of athird exemplary configuration of the fourth embodiment differs fromdigital/analog conversion device 12# shown in FIG. 12 in that the formerincludes a charge pump circuit 131# instead of charge pump circuit 130#.Charge pump circuit 131# differs from charge pump circuit 130# in thatthe former includes a bias circuit 141# instead of bias circuit 140#.Bias circuit 141# differs from bias circuit 140# shown in FIG. 12 inthat current-limiting element 42 is constituted of constant currentsource 44.

[0126] In other words, digital/analog conversion device 13# isconfigured correspondingly to digital/analog conversion device 13 shownin FIG. 8 and has the opposite polarity with respect to output voltageVNo. Namely, differences between digital/analog conversion devices #12and #13 are similar to those between digital/analog conversion devices12 and 13. Therefore, digital/analog conversion device 13# can provide,like digital/analog conversion device 13 of the modification of thesecond embodiment, in addition to the effect of digital/analogconversion device 12# shown in FIG. 12, an effect that output voltageVNo can accurately be set by further reducing the temperaturedependency.

[0127] Referring to FIG. 14, a digital/analog conversion device 14# of afourth exemplary configuration of the fourth embodiment differs fromdigital/analog conversion device 12# shown in FIG. 12 in that the formerincludes a charge pump circuit 132# instead of charge pump circuit 130#.Charge pump circuit 132# differs from charge pump circuit 130# in thatthe former includes a bias circuit 142# instead of bias circuit 140#.

[0128] Bias circuit 142# differs from bias circuit 140# shown in FIG. 12in that the former further includes an n-type transistor 45# connectedbetween p-type transistor 41# and node N2 and a p-type transistor 46#connected between node N3 and n-type transistor 43#. N-type transistor45# is diode-connected and has its gate connected to node N2. Similarly,p-type transistor 46# is diode-connected and has its gate connected tonode N3.

[0129] Digital/analog conversion device 14# has its configurationsimilar to that of digital/analog conversion device 12# shown in FIG. 12except for the above-described differences, and the detailed descriptionthereof is not repeated here. In other words, digital/analog conversiondevice 14# is configured correspondingly to digital/analog conversiondevice 14 shown in FIG. 9 and has the opposite polarity with respect tooutput voltage VNo.

[0130] Thus, like digital/analog conversion device 14 of the thirdembodiment, digital/analog conversion device 14# provides, in additionto the effect of digital/analog conversion device 10# in FIG. 11, aneffect that output voltage VNo can more accurately be generated byeliminating the influence of the manufacturing-related variation of thethreshold voltages of the transistors. Further, since ΔV can easily beensured, the range of the output voltage can be expanded.

[0131] Referring to FIG. 15, a digital/analog conversion device 15# of afifth exemplary configuration of the fourth embodiment differs fromdigital/analog conversion device 14# shown in FIG. 14 in that the formerincludes a charge pump circuit 133# instead of charge pump circuit 132#.Charge pump circuit 133# differs from charge pump circuit 132# in thatthe former includes a bias circuit 143# instead of bias circuit 142#.Bias circuit 143# differs from bias circuit 142# shown in FIG. 12 inthat current-limiting element 42 is constituted of constant currentsource 44.

[0132] In other words, digital/analog conversion device 15# isconfigured correspondingly to digital/analog conversion device 15 shownin FIG. 10 and has the opposite polarity with respect to output voltageVNo. Namely, differences between digital/analog conversion devices 14#and 15# are similar to those between digital/analog conversion devices14 and 15. Therefore, digital/analog conversion device 15# provides,like digital/analog conversion device 15 of the modification of thethird embodiment, in addition to the effect of digital/analog conversiondevice 14# in FIG. 14, an effect that output voltage VNo can moreaccurately be set by further reducing the temperature dependency.

[0133] Fifth Embodiment

[0134] Regarding the digital/analog conversion devices of the first tothird embodiments and respective modifications as well as the fourthembodiment, the level of output voltage VNo is influenced by capacitorvalue Cp of the pump capacitor and capacitor value Co of the outputcapacitor. Then, in order to precisely set output voltage VNo, it ispreferable that these capacitor values Cp and Co are adjustable.

[0135] Referring to FIG. 16, a digital/analog conversion device 16 of afifth embodiment includes a pulse number control circuit 20 (or 20#) aswell as a pump capacitor 32 and a circuit block 35 that constitute acharge pump circuit, and generates, on an output node No to which anoutput capacitor 5 is connected, output voltage VNo which is an analogvoltage generated according to input digital data. Circuit block 35generally represents a circuit portion corresponding to any of theabove-described charge pump circuits 30 and 131-133 (or 30# and131#-133#) without pump capacitor 32.

[0136] In the configuration of the fifth embodiment, pump capacitor 32and output capacitor 5 are each configured to be finely adjustable inresponse to an external input. Pump capacitor 32 includes a plurality ofadjustment units 36 connected in parallel between nodes N1 and N2.Adjustment units 36 each include a unit capacitor SCa and a link elementLKa connected in series between nodes N1 and N2.

[0137] Similarly, output capacitor 5 includes a plurality of adjustmentunits 37 connected in parallel between a predetermined voltage Vss andoutput node No. Adjustment units 37 each include a unit capacitor SCband a link element LKb connected in series between predetermined voltageVss and output node No.

[0138] In response to a program input from the outside of adjustmentunits 36, link elements LKa each can independently select whether or notto establish an electrical path including its correlated unit capacitorSCa between nodes N1 and N2. Similarly, in response to a program inputfrom the outside of adjustment units 37, link elements LKb each canindependently select whether or not to establish an electrical pathincluding its correlated unit capacitor SCb between output node No andpredetermined voltage Vss.

[0139] As link elements LKa and LKb each, a laser fuse may be employedthat is blown in response to laser radiation given as a program input,or an electric fuse may be employed that is blown in response to a highvoltage applied as a program input, for example. Alternatively, the linkelement may be constituted of an antifuse element changing from anonconductive state to a conductive state in response to a high voltageapplied as a program input for breaking an insulating film.

[0140] The digital/analog conversion device of the fifth embodiment isthus configured to adjust in a stepwise manner capacitance Cp of pumpcapacitor 32 and capacitance Co of output capacitor 5 that influence thelevel of output voltage VNo. Accordingly, a more accurate analog voltagecan be generated by a fine adjustment of the level of output voltageVNo.

[0141] Sixth Embodiment

[0142] According to a sixth embodiment, a description is given of aconfiguration for providing a gray-level voltage for a display device bymeans of the digital/analog conversion devices using the charge pumpoperation as described in connection with the first to fifth embodimentsand respective modifications.

[0143]FIG. 17 is a block diagram showing an entire configuration of adisplay device according to the sixth embodiment.

[0144] Referring to FIG. 17, display device 200 of the sixth embodimentincludes a display panel unit 220, a gate driver 230 and a source driver240. Although the display device shown in FIG. 17 is configured tointegrate gate driver 230 and source driver 240 with display panel unit220, the drivers may be provided as external circuits of display panelunit 220.

[0145] Display panel unit 220 includes a plurality of pixel circuits 225arranged in rows and columns. Gate lines GL are arranged correspondinglyto the rows of the pixel circuits (hereinafter referred to as “pixelrow(s)”), and data lines DL are arranged correspondingly to the columnsof the pixel circuits (hereinafter referred to as “pixel column(s)”).FIG. 17 representatively shows pixel circuits of a first row and firstand second columns and corresponding gate line GL1 and data lines DL1and DL2.

[0146] Pixel circuits 225 each include a switch element 226 providedbetween its corresponding data line DL and a pixel node Np, a holdingcapacitor 227 and a liquid-crystal display element 228 connected inparallel between pixel node Np and a common electrode node NC. Accordingto a voltage difference between pixel node Np and common electrode nodeNC, the orientation of liquid-crystal molecules in liquid-crystaldisplay element 228 changes. In response to this change, the brightnessof display of liquid-crystal display element 228 changes. . Thus,according to a display voltage written to pixel node Np via data line DLand switch element 226, the brightness of each pixel circuit can becontrolled. Switch element 226 is constituted, for example, of an n-typetransistor.

[0147] Gate driver 230 activates gate lines GL one by one based on apredetermined cycle. The gate of switch element 226 is connected to itscorresponding gate line GL. Thus, in a period during which thecorresponding gate line GL is activated (H level), pixel node Np isconnected to its corresponding data line DL. Switch element 226 isgenerally constituted of a TFT formed on an insulating substrate (e.g.glass substrate, resin substrate) on which liquid-crystal element 228 isalso formed. The display voltage transmitted to pixel node Np istransmitted by holding capacitor 227.

[0148] Alternatively, pixel circuit 225 in FIG. 17 may be replaced witha pixel circuit 225# including a current-driven type light-emittingelement shown in FIG. 18.

[0149] Referring to FIG. 18, pixel circuit 225# includes a switchelement 226, a holding capacitor 227#, an EL (Electro-Luminescence)element 228# which is a typical example of the current-driven typelight-emitting element, and a current drive transistor 229. As in pixelcircuit 255, switch element 226 is provided between its correspondingdata line DL and pixel node Np and has its gate connected to itscorresponding gate line GL. Holding capacitor 227# is connected betweenpixel node Np and voltage Vdd. EL element 228# and current drivetransistor 229 are connected in series between voltage Vdd and voltageVss. Current drive transistor 229 is, for example, constituted of ap-type TFT. Generally, switch element 226 and current drive transistor229 are formed on the same insulating substrate on which EL element 228#is also formed.

[0150] Switch element 226 connects, in a period during which itscorresponding gate line GL is activated (H level), pixel node Np to dataline DL. Accordingly, a display voltage on data line DL is transmittedto pixel node Np. The voltage on pixel node Np is held by holdingcapacitor 227#;

[0151] Current drive transistor 229 has its gate connected to pixel nodeNp and supplies, to EL element 228#,.a current Iel according to thevoltage on pixel node Np, namely the display voltage (gray-levelvoltage) transmitted from the data line. The display brightness of ELelement 228# changes according to supplied pass current Iel. Thus, withpixel circuit 225# as well, the display voltage to be applied to thepixel circuit can be set in a stepwise manner so that the brightness ofthe EL element represents a gray level.

[0152] It will be clearly understood from the following description thatthe sixth embodiment is directed to peripheral circuitry that generatesa display voltage (gray-level voltage) to be supplied to each pixelcircuit. Therefore, the present invention is applicable to any displaydevice having pixel circuits each indicating a brightness according tothe gray-level voltage, without restrictions on the configuration of thepixel circuits.

[0153] Referring again to FIG. 17, source driver 240 outputs, to dataline DL, a display voltage which is set in a stepwise manner by displaydata SIG of n bits. The sixth embodiment is also described by taking anexample that n is 4 (n=4), namely display data SIG is constituted ofdata bits D0-D3. In the sixth embodiment as well, it is supposed thatdata bit D0 is the least significant bit (LSB) and data bit D3 is themost significant bit (MSB). Then, display device 200 of the sixthembodiment can display 2⁴=16 gray levels by each pixel circuit accordingto display data SIG of 4 bits.

[0154] Source driver 240 includes a shift register 250, data latchcircuits 252 and 254 and a display-voltage generation circuit 270.

[0155] Display data SIG is generated serially according to the displaybrightness of each pixel circuit 225. In other words, data bits D0-D3 ata certain timing represent the display brightness of one pixel circuit225 within display panel unit 220. Shift register 250 instructs datalatch circuit 252 to take data bits D0-D3 at a timing in synchronizationwith a predetermined cycle based on which generating of display data SIGis changed. Data latch circuit 252 successively takes and holds displaydata SIG corresponding to one pixel row that is generated serially.

[0156] At a timing at which display data SIG corresponding to one pixelrow is taken by data latch circuit 252, the group of display datalatched by data latch circuit is transmitted to data latch circuit 254in response to activation of a latch signal LT.

[0157] Display-voltage generation circuit 270 includes gray-levelvoltage generation circuits 280 provided correspondingly to respectivedata lines DL. Gray-level voltage generation circuits 280 each output,to output node No, a gray-level voltage obtained by digital-analogconversion of corresponding data bits D0-D3 held in data latch circuit254, as a display voltage. Output node No of each gray-level voltagegeneration circuit is connected to a corresponding data line DL. Forexample, output nodes No1 and No2 of gray-level voltage generationcircuits 280 provided correspondingly to respective data lines DL1 andDL2 shown in FIG. 17 are connected to data lines DL1 and DL2respectively.

[0158] Gray-level voltage generation circuits 280 each include a pulsenumber control circuit 290 and a charge pump circuit 295. As pulsenumber control circuit 290, any of pulse number control circuits 20 and20# shown respectively in FIGS. 1 and 6 for example may be employed. Thepulse number control circuit receives successively provided pulses CPand then inputs pulses CP# of a number according to corresponding databits D0-D3 to charge pump circuit 295. In other words, the number ofpulses CP# that are input to charge pump circuit 295 is set according toa value obtained by performing digital-analog conversion on data bitsD0-D3.

[0159] In response to each input of pulses CP# from pulse number controlcircuit 290, charge pump circuit 295 changes the voltage on output nodeNo in a stepwise manner. As charge pump circuit 295, any of charge pumpcircuits 30 and 131-133 as well as charge pump circuits 30# and131#-133# described in connection with the first to fifth embodimentsand respective modifications may be employed.

[0160] With this configuration, a display voltage for displaying a graylevel can be generated by using the charge pump circuit with low powerconsumption. In particular, any of the charge pump circuits of the firstto fifth embodiments and respective modifications may be used as chargepump circuit 295 to precisely generate the gray-level voltage.Alternatively, depending on the precision with which a requiredgray-level voltage is set or the circuit area, any charge pump circuithaving a common configuration without the arrangement of the biascircuits described in connection with the first to fifth embodiments andrespective modifications may be applied.

[0161] However, particularly for a display device having liquid-crystaldisplay elements as respective pixel circuits (hereinafter referred toas “liquid-crystal display device”), it is necessary to address theissue of the temperature dependency of a parasitic capacitance of dataline DL corresponding to the output capacitor of the charge pumpcircuit.

[0162]FIG. 19 is a cross-sectional view illustrating a parasiticcapacitance of a data line that is an output capacitor of a charge pumpcircuit in a liquid-crystal display device.

[0163] Referring to FIG. 19, the liquid-crystal display device is formedon a glass substrate 300 which is a typical example of an insulatingsubstrate. On glass substrate 300, an insulating layer 340, a metalinterconnection layer 320, an insulating layer 350 and a liquid-crystallayer 360 are deposited in this order and a common electrode 330 isprovided on the upper surface of liquid-crystal layer 360. Data line DLshown in FIG. 17 is provided in metal interconnection layer 320. Dataline DL is typically formed of an aluminum interconnection. Commonelectrode 330 corresponds to common electrode node NC shown in FIG. 17.

[0164] Since gate line GL shown in FIG. 17 is used as a gate electrodeof the TFT (not shown) formed on glass substrate 300, gate line GL isformed in a metal interconnection layer 310 provided in the middle ofinsulating layer 340. Gate line GL is typically formed of an aluminuminterconnection.

[0165] Here, capacitor Ca corresponds to a parasitic capacitance betweendata line DL and gate line GL and capacitors Cb and Cc correspondrespectively to parasitic capacitances in insulating layer 350 andliquid-crystal layer 360 between data line DL and common electrode 330.Then, the parasitic capacitance of data line DL, namely output capacitorCo of the charge pump circuit, is represented by the sum of capacitancesof capacitors Cb and Cc connected in series and capacitor Ca.

[0166] Capacitors Ca and Cb in the insulating layers have almost notemperature dependency while capacitor Cc in the liquid-crystal layervaries depending on temperature. Therefore, the output capacitor (Co) ofthe charge pump circuit has temperature dependency.

[0167] Accordingly, as seen from Equations (1) and (4) above, outputvoltage VNo of the charge pump circuit, namely the gray-level voltagesupplied to the pixel circuit varies depending on temperature.

[0168] Then, for the display device of the sixth embodiment, a pumpcapacitor in the charge pump circuit, for example, pump capacitor 32 inthe charge pump circuits as described in connection with the first tofifth embodiments and respective modifications, is formed in a similarmanner to that in which the peripheral region of data line DL isconfigured as detailed below so as to reduce the variation of thegray-level voltage.

[0169]FIG. 20 conceptually shows how the pump capacitor of the sixthembodiment is formed.

[0170] Referring to FIG. 20, in the configuration of the sixthembodiment, pump capacitor 32 in the charge pump circuit is implementedby parallel connection of a capacitor Ca# between nodes N1 and N2 andcapacitors Cb# and Cc# connected in series to nodes N1 and N2. Further,these capacitors Ca#-Cc# are configured similarly to capacitors Ca-Ccrespectively shown in FIG. 19.

[0171]FIG. 21 shows a first exemplary configuration of the pumpcapacitor of the sixth embodiment.

[0172] Referring to FIG. 21, in the region where pump capacitor 32 isformed, insulating layers 340 and 350 and liquid-crystal layer 360 areformed as the region where data line DL is provided (liquid-crystalpanel unit 220 in FIG. 17). Then, pump capacitor 32 is formed betweenelectrodes 380 and 382 corresponding respectively to nodes N1 and N2formed in metal interconnection layer 320 where data line DL is alsoprovided. Preferably, electrodes 380 and 382 are each made of the samematerial as that of data line DL.

[0173] Pump capacitor 32 includes capacitors Ca#-Cc# configuredsimilarly to capacitors Ca-Cc constituting the output capacitor. Inorder to form capacitor Ca#, a dummy electrode 315 is formed in metalinterconnection layer 310 where gate line GL is also formed so thatdummy electrode 315 is opposite to electrode 380 with insulating layer340 therebetween. Further, dummy electrode 315 is connected electricallyto electrode 382 by a contact 383 formed in a through hole provided ininsulating layer 340.

[0174] In the layer where common electrode 330 is provided, a dummyelectrode 332 is formed opposite to electrode 380 with insulating layer350 and liquid-crystal layer 360 therebetween. Then, between dummyelectrode 332 and electrode 380, series-connected capacitors Cb# and Cc#corresponding respectively to parasitic capacitances of insulating layer350 and liquid-crystal layer 360 are present.

[0175] Further, electrode 382 is connected to dummy electrode 332 by acontact electrode 384 and a conductive resin 386 constituting a contactportion formed in the through hole provided in insulating layer 350 andliquid-crystal layer 360. Contact electrode 384 is formed of an aluminumor ITO (Indium-Tin-Oxide) film. Dummy electrode 332 and contactelectrode 384 are connected by pressure with conductive resin 386.Further, dummy electrode 332 is electrically disconnected by aninsulating film 370 from at least common electrode 330.

[0176] With this configuration, pump capacitor 32 is formed betweenelectrodes 380 and 382 by combination of capacitors Ca#-Cc#, like theparasitic capacitor of data line DL (i.e., output capacitor of thecharge pump circuit). Respective areas of dummy electrodes 315 and 332and electrodes 380 and 382 are designed so that the syntheticcapacitance of capacitor components Ca#-Cc#, namely“Ca#+Cb#·Cc#/(Cb#+Cc#)” is equal to capacitance Cp.

[0177] With the above-described configuration, the pump capacitor isprovided to allow capacitance Cp of the pump capacitor and capacitanceCo of the output capacitor to have the same temperature dependencies.Then, even if capacitances Cp and Co in Equations (1) and (4) forexample have temperature dependencies, the temperature dependenciescancel out by the ratio of Co/Cp, and thus the levels of voltages V2 andVB, namely the level of output voltage VNo does not have a large degreeof temperature dependency. In this way, the temperature dependency canbe eliminated to generate a gray-level voltage precisely by using thecharge pump circuit.

[0178]FIG. 22 shows a second exemplary configuration of a pump capacitorof a sixth embodiment.

[0179] Referring to FIG. 22 as compared with FIG. 21, in the secondexemplary configuration, a dummy electrode 332 is formed in the layerwhere common electrode 330 is formed so that dummy electrode 332 isopposite to both of electrodes 380 and 382 with insulating layer 350 andliquid-crystal layer 360 therebetween. Further, there is no electricalcontact between dummy electrode 332 and electrode 382. In other words,there is no contact electrode 384 and conductive resin 386 shown in FIG.21. In addition, an insulating film 372 for electrically disconnectingdummy electrode 332 from other nodes and interconnections for example isprovided as required, since dummy electrode 332 should be in anelectrically floating state.

[0180] Thus, between electrodes 380 and 382 and dummy electrode 332,capacitor 2Cb# that is a parasitic capacitance of insulating layer 350and capacitor 2Cc# that is a parasitic capacitance of liquid-crystaldisplay 360 are connected in series, and these series-connectedcapacitors are connected in parallel. These capacitors 2Cb# and 2Cc# aretwice as large as capacitors Cb# and Cc# shown in FIG. 21 incapacitance.

[0181] Between electrode 380 and dummy electrode 315, capacitor Ca# isformed to have the same configuration as that of FIG. 21.

[0182] Accordingly, the capacitor value between electrodes 380 and 382,namely between nodes N1 and N2, is Ca#+Cb#·Cc#/(Cb#+Cc#), which is thesame as that of the exemplary configuration shown in FIG. 21. The pumpcapacitor of the charge pump circuit and the output capacitor can beconfigured similarly as shown in FIG. 21 to eliminate the temperaturedependency and generate a gray-level voltage precisely. Further,regarding the exemplary configuration shown in FIG. 22, the attachmentby pressure with the conductive resin having low dimensional accuracy isunnecessary, so that production can be facilitated and improvement ofthe yield can be expected.

[0183] Seventh Embodiment

[0184] According to a seventh embodiment, a description is givenregarding a configuration of a display device that can speedily generatea gray-level voltage on data line DL.

[0185] Referring to FIG. 23, a gray-level voltage generation circuit 400of the seventh embodiment includes a pulse control unit 405, a pulsenumber control circuit 292, switch units 410 and 420, an increasing-typecharge pump circuit (hereinafter upcharge pump circuit) 295U and adecreasing-type charge pump circuit (hereinafter downcharge pumpcircuit) 295D.

[0186] Pulse control unit 405 includes an inverter 406 inverting pulseCP to output an inverted pulse /CP and switches 407 and 408 that arecomplementarily turned on/off in response to data bit D3 of the mostsignificant digit.

[0187] Pulse number control circuit 292 receives pulse CP or invertedpulse /CP transmitted to a node N4 by pulse control unit 405 to outputpulses CP or inverted pulses /CP of a number according to data bitsD0-D3 to a node N5.

[0188] Switch unit 410 includes a switch 412 provided between node N5and upcharge pump circuit 295U and a switch 414 provided between node N5and downcharge pump circuit 295D. Switch unit 420 includes a switch 422provided between an output node of upcharge pump circuit 295U and dataline DL and a switch 424 provided between an output node of downchargepump circuit 295D and data line DL.

[0189] In generating a gray-level voltage, switches 412 and 422 areturned on when data bit D3 is “1” and turned off when data bit D3 is“0”. According to data bit D3, switches 414 and 424 are turned on/offcomplementarily to switches 412 and 422.

[0190] Each time one pulse CP is input, upcharge pump circuit 295Uincreases a voltage on the output node by ΔV in a stepwise manner. Inother words, as upcharge pump circuit 295U, any of upcharge pumpcircuits 30 and 131-133 described in connection with the first to thirdembodiments and respective modifications may be employed.

[0191] Each time one inverted pulse /CP is input, downcharge pumpcircuit 295D decreases a voltage on the output node by ΔV in a stepwisemanner. In other words, as downcharge pump circuit 295D, any of chargepump circuits 30# and 131#-133# described in connection with the fourthembodiment may be used.

[0192] Alternatively, depending on the precision with which a requiredgray-level voltage is set and the circuit area, a charge pump circuit ofa common configuration that has no bias circuit as described inconnection with the first to fifth embodiments and respectivemodifications may be used as charge pump circuits 295U and 295D each.

[0193] To data line DL, a pixel circuit 225 (or 225#) corresponding to aselected gate line GL is connected as described in connection with FIG.17.

[0194] Further, for data line DL, an intermediate-voltage generationcircuit 440 and a precharge switch 445 connecting intermediate-voltagegeneration circuit 440 and data line DL in response to a prechargesignal PE are provided.

[0195] Intermediate-voltage generation circuit 440 generates anintermediate voltage Vm between high voltage VDH and low voltage VDLcorresponding respectively to the maximum and minimum levels of thegray-level voltage. More specifically, supposing that high voltage VDHis a gray-level voltage corresponding to (D3, D2, D1, D0)=(1, 1, 1, 1)and low voltage VDL is a gray-level voltage corresponding to (D3, D2,D1, D0)=(0, 0, 0, 0), precharge voltage Vm is set to a gray-levelvoltage corresponding to the intermediate level (D3, D2, D1, D0)=(1, 0,0, 0).

[0196] In response to precharge signal PE, precharge switch 445 isturned on before a gray-level voltage is generated so as to prechargedata line DL to intermediate voltage Vm. Precharge switch 445 is turnedoff when the gray-level voltage is generated, namely at the timing whencharge pump circuit 295U or 295D is connected by switch unit 420 to dataline DL.

[0197]FIG. 24 is a circuit diagram showing a configuration of pulsenumber control circuit 292 shown in FIG. 23.

[0198] Referring go FIG. 24, pulse number control circuit 292 differsfrom pulse number control circuit 20# shown in FIG. 6 in that the formerincludes a switch control circuit 297 instead of switch control circuit27#. Switch elements 22-25 and 22#-25# are provided for controllingconnection between nodes N4 and N5. Switch elements 22#-25# are turnedon/off in response to respective control signals D0#-D3# from switchcontrol circuit 297. Switch elements 22-24 are turned on/off in responseto respective control signals C0-C2 and switch element 25 is turnedon/off in response to control signal Co.

[0199] Switch control circuit 297 includes a multiplexer 293 thatoutputs control signals D0#-D2#, and an inverter 294 that outputscontrol signal D3#. Multiplexer 293 receives data bits D0-D2 and databits /D0-/D2 inverted by the inverter and outputs, when data bit D3 is“1”, data bits D0-D2 as control signals D0#-D2# while outputs, when databit D3 is “0”, inverted data bits /D0-/D2 as control signals D0#-D2#.Inverter 294 outputs inverted data bit /D3 as control signal D3#.

[0200] Referring again to FIG. 23, when data bit D3 is “1”, pulses CPare output from pulse control unit 405 to node N4. Pulse number controlcircuit 292 generates control signals D0#-D3# with the configurationshown in FIG. 24 so that pulses CP of a number corresponding to adifference between a gray-level voltage to be generated and intermediatevoltage Vm are transmitted to node N5.

[0201] Pulses CP transmitted to node N5 are input via switch 412 tocharge pump circuit 295U. The output node N6 of charge pump circuit 295Uis connected by switch 422 to data line DL. No inverted pulse /CP isinput to charge pump circuit 295D and the output node N7 thereof isdisconnected from data line DL. As a result, the voltage on data lineDL, namely gray-level voltage, increases from intermediate voltage Vm toa voltage corresponding to data bits D0-D3 according to the number ofpulses CP that. are input to charge pump circuit 295U.

[0202] On the other hand, when data bit D3 is “0”, inverted pulses /CPare output from pulse control unit 405 to node N4. Pulse number controlcircuit 292 generates control signals D0#-D3# so that inverted pulses/CP of a number corresponding to a difference between a gray-levelvoltage to be generated and intermediate voltage Vm are transmitted tonode N5.

[0203] Inverted pulses /CP transmitted to node N5 are input to chargepump circuit 295D via switch 414. The output node N7 of charge pumpcircuit 295D is connected by switch 424 to data line DL. No pulse CP isinput to charge pump circuit 295U and its output node N6 is disconnectedfrom data line DL. As a result, the voltage on data line DL (gray-levelvoltage) decreases from intermediate voltage Vm to a voltagecorresponding to data bits D0-D3 according to the number of invertedpulses /CP input to charge pump circuit 295D.

[0204] In this way, with the configuration of the seventh embodiment,data line DL is precharged to intermediate voltage Vm and thereafter theupcharge pump circuit and the downcharge pump circuit are selectivelyoperated to generate a gray-level voltage. Thus, as compared with theconfiguration in which only one of the upcharge pump circuit and thedowncharge pump circuit is employed, the gray-level voltage can begenerated more speedily.

[0205] Modification of the Seventh Embodiment

[0206]FIG. 25 is a circuit diagram showing an exemplary configuration ofa gray-level voltage generation circuit according to a modification ofthe seventh embodiment.

[0207] Referring to FIG. 25, the configuration of the modification ofthe seventh embodiment differs from the that of the seventh embodimentshown in FIG. 23 in that the former includes a gray-level voltagegeneration circuit 400# instead of gray-level voltage generation circuit400 and includes a precharge circuit 450 instead of intermediate-voltagegeneration circuit 440 and precharge switch 445.

[0208] Precharge circuit 450 includes a switch 452 provided between highvoltage VDH and data line DL and a switch 454 provided between data lineDL and low voltage VDL. In response to signals PE3 and /PE3respectively, switches 452 and 454 are complementarily turned on/offaccording to data bit D3 in the period during which precharge switch 445shown in FIG. 23 is turned on.

[0209] Gray-level voltage generation circuit 400# differs fromgray-level voltage generation circuit 400 shown in FIG. 23 in that theformer includes a pulse number control circuit 296 instead of pulsenumber control circuit 292. Further, switches 407, 412, 422 and switches408, 414, 424 are turned on/off in the opposite manner to those ofgray-level voltage generation circuit 400. Specifically, when data bitD3 is “1”, switches 407, 412 and 422 are each turned off while switches408, 414 and 424 are each turned on. When data bit D3 is “0”, switches407, 412 and 422 are each turned on while switches 408, 414 and 424 areeach turned off.

[0210]FIG. 26 is a circuit diagram showing a configuration of pulsenumber control circuit 296 shown in FIG. 25.

[0211] Referring to FIG. 26, pulse number control circuit 296 differsfrom pulse number control circuit 292 shown in FIG. 24 in that theformer does not require arrangement of switch elements 25 and 25# fordata bit D3 and includes a switch control circuit 297# instead of switchcontrol circuit 297.

[0212] Switch control circuit 297# includes a multiplexer 293 generatingcontrol signals D0#-D2#. In the opposite manner to that shown in FIG.24, multiplexer 293 outputs inverted data bits /D0-/D2 as controlsignals D0#-D2# when data bit D3 is “1” and outputs data bits D0-D2 ascontrol signals D0#-D2# when data bit D3 is “0”.

[0213] Switches 22#-24# are turned on/off in response to respectivecontrol signals D0#-D2# from switch control circuit 297# and switches22-24 are turned on/off in response to respective control signals C0-C2.

[0214] Referring again to FIG. 25, when data bit D3 is “1”, prechargecircuit 450 precharges data line DL to high voltage VDH before agray-level voltage is generated. In this state, pulse control unit 405outputs inverted pulses /CP to node N4. Pulse number control circuit 296generates control signals D0#-D2# with the configuration shown in FIG.26 to transmit to output node N5 inverted pulses /CP of a numbercorresponding to a difference between a gray-level voltage to begenerated and high voltage VDH.

[0215] Inverted pulses /CP transmitted to node N5 are input to chargepump circuit 295D via switch 414. The output node N7 of charge pumpcircuit 295D is connected to data line DL by switch 424. No pulse CP isinput to charge pump circuit 295U and its output node N6 is disconnectedfrom data line DL. Then, the voltage on data line DL (gray-levelvoltage) decreases from high voltage VDH to a voltage corresponding todata bits D0-D3 according to the number of inverted pulses /CP input tocharge pump circuit 295D.

[0216] When data bit D3 is “0”, precharge circuit 450 precharges dataline DL to low voltage VDL before a gray-level voltage is generated. Inthis state, pulse control unit 405 outputs pulses CP to node N4. Pulsenumber control circuit 296 generates control signals D0#-D2# so thatpulses CP of a number corresponding to a difference between a gray-levelvoltage to be generated and low voltage VDL are transmitted to node N5.

[0217] Pulses CP transmitted to node N5 are input via switch 412 tocharge pump circuit 295U. The output node N6 of charge pump circuit 295Uis connected by switch 422 to data line DL. No inverted pulse/CP isinput to charge pump circuit 295D and its output node N7 is disconnectedfrom data line DL. Accordingly, the voltage on data line DL (gray-levelvoltage) is increased from low voltage VDL to a voltage corresponding todata bits D0-D3 according to the number of pulses CP input to chargepump circuit 295U.

[0218] As discussed above, with the configuration of the modification ofthe seventh embodiment, a combination of the upcharge pump circuit andthe downcharge pump circuit can be used to generate a gray-level voltageand change a precharge voltage on a data line according to a specifiedbit of display data. Thus, as compared with the configuration of theseventh embodiment, the gray-level voltage can be generated morespeedily.

[0219] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A digital/analog conversion device outputting ananalog voltage according to digital data of a plurality of weightedbits, comprising: a pulse number control circuit supplying, to a firstnode, pulses of a number according to said digital data, said pulsesincluding a first transition edge changing from an initial level to apredetermined level and a second transition edge returning from saidpredetermined level to said initial level; and a charge pump circuitchanging, in a stepwise manner, each time one of said pulses is suppliedto said first node, a voltage on an output node having an outputcapacitor connected thereto, said charge pump circuit including a pumpcapacitor connected between a second node and said first node, a switchelement connected between said second node and said output node to beturned on at a timing at which said first transition edge of each ofsaid pulses is transmitted to said first node and turned off at a timingat which said second transition edge thereof is transmitted to saidfirst node and a bias circuit changing, according to the change of thevoltage on said output node, a voltage on said second node with the samepolarity as that of the change of the voltage on said output node. 2.The digital/analog conversion device according to claim 1, wherein saidpulse number control circuit includes a switch circuit provided betweena pulse node to which said pulses are successively supplied and saidfirst node and transmitting, when said switch circuit is turned on, saidpulses from said pulse node to said first node and a switch controlcircuit turning on said switch circuit for a period of time according tosaid digital data.
 3. The digital/analog conversion device according toclaim 1, further comprising a precharge circuit for setting said firstnode, said second node and said output node each to a predeterminedprecharge voltage before said analog voltage is output.
 4. Thedigital/analog conversion device according to claim 3, wherein saidprecharge voltage corresponds to a minimum level in a range over whichsaid analog voltage is controlled, and said charge pump circuitincreases in a stepwise manner the voltage on said output node each timesaid pulse is transmitted to said first node.
 5. The digital/analogconversion device according to claim 3, wherein said precharge voltagecorresponds to a maximum level in a range over which said analog voltageis controlled, and said charge pump circuit decreases in a stepwisemanner the voltage on said output node each time said pulse istransmitted to said first node.
 6. The digital/analog conversion deviceaccording to claim 1, wherein said bias circuit includes a transistorelectrically connected between a power-supply node to which apredetermined voltage is supplied and said second node, and saidtransistor has its gate connected to said output node.
 7. Thedigital/analog conversion device according to claim 1, wherein said biascircuit includes a first transistor of a first conductivity typeelectrically connected between a first power-supply node to which afirst predetermined voltage is supplied and said second node, acurrent-limiting element connected between a second power-supply node towhich a second predetermined voltage is supplied and a third node and asecond transistor of a conductivity type opposite to said firstconductivity type connected between a third power-supply node to which athird predetermined voltage is supplied and said third node, said firsttransistor has its gate connected to said third node, and said secondtransistor has its gate connected to said output node.
 8. Thedigital/analog conversion device according to claim 7, wherein saidcurrent-limiting element is constituted of a constant-current sourcesupplying a constant current regardless of a voltage difference betweensaid third power-supply node and said third node.
 9. The digital/analogconversion device according to claim 1, wherein said bias circuitincludes a first transistor of a first conductivity type and a secondtransistor of a second conductivity type opposite to said firstconductivity type that are connected in series between a firstpower-supply node to which a first predetermined voltage is supplied andsaid second node, a current-limiting element connected between a secondpower-supply node to which a second predetermined voltage is suppliedand a third node and a third transistor of said first conductivity typeand a fourth transistor of said second conductivity type connected inseries between a third power-supply node to which a third predeterminedvoltage is supplied and said third node, said first transistor has itsgate connected to said third node, said fourth transistor has its gateconnected to said output node, and said second and third transistors areeach diode-connected.
 10. The digital/analog conversion device accordingto claim 9, wherein said current-limiting element is constituted of aconstant-current source supplying a constant current regardless of avoltage difference between said third power-supply node and said thirdnode.
 11. The digital/analog conversion device according to claim 1,wherein said pump capacitor includes a plurality of first adjustmentunits connected in parallel between said first node and said secondnode, said output capacitor includes a plurality of second adjustmentunits connected in parallel with respect to said output node, saidplurality of first adjustment units and said plurality of secondadjustment units each include a unit capacitor and a link elementconnected in series, and said link element is configured to be able toselect, according to an input from the outside of said first and secondadjustment units, whether or not to establish an electrical pathincluding said unit capacitor correlated with said link element.
 12. Adisplay device displaying a gray level based on display data constitutedof weighted n bits where n is an integer of at least two, comprising: aplurality of pixel circuits each indicating a brightness according to asupplied voltage; a selection line for selecting said plurality of pixelcircuits; a data line connected to said plurality of pixel circuits; anda gray-level voltage generation circuit for supplying to said data linea gray-level voltage that is an analog voltage according to said displaydata, said gray-level voltage generation circuit including a pulsenumber control circuit supplying, to a first node, pulses of a numberaccording to said display data, said pulses including a first transitionedge changing from an initial level to a predetermined level and asecond transition edge returning from said predetermined level to saidinitial level and a charge pump circuit changing, in a stepwise manner,each time one of said pulses is supplied to said first node, a voltageon an output node connected to said data line.
 13. The display deviceaccording to claim 12, wherein said charge pump circuit includes a pumpcapacitor connected between a second node and said first node, a switchelement connected between said second node and said output node to beturned on at a timing at which said first transition edge of each ofsaid pulses is transmitted to said first node and turned off at a timingat which said second transition edge thereof is transmitted to saidfirst node and a bias circuit changing, according to the change of thevoltage on said output node, a voltage on said second node with the samepolarity as that of the change of the voltage on said output node. 14.The display device according to claim 12, wherein said charge pumpcircuit includes a pump capacitor for transmitting by capacitivecoupling a voltage change on said first node caused upon said pulse issupplied, and said pump capacitor is formed to have a similarconfiguration to that of a parasitic capacitance of said data line. 15.The display device according to claim 14, wherein said pixel circuitseach include a liquid-crystal element connected between a commonelectrode and a pixel node connected to said data line according to astate of said selection line, a first insulating layer and aliquid-crystal layer having said liquid-crystal element formed thereinare deposited between a first metal interconnection layer having saiddata line provided therein and a layer having said common electrodeformed therein, a second insulating layer is present between a secondmetal interconnection layer having said selection line provided thereinand said first metal interconnection layer, said pump capacitor includesa first electrode and a second electrode provided in said first metalinterconnection layer, a first dummy electrode formed in the layer inwhich said common electrode is formed in such a manner that said firstdummy electrode is opposite to said first electrode with saidliquid-crystal layer and said first insulating layer therebetween, asecond dummy electrode formed in said second metal interconnection layerin such a manner that said second dummy electrode is opposite to saidfirst electrode with said second insulating layer therebetween, a firstcontact portion formed in a through hole provided in said liquid-crystallayer and said first insulating layer for electrically connecting saidfirst dummy electrode and said second electrode, and a second contactportion formed in a through hole provided in said second insulatinglayer for electrically connecting said second dummy electrode and saidsecond electrode, and said pump capacitor has its capacitancerepresented by a synthetic capacitance value between said firstelectrode and said second electrode.
 16. The display device according toclaim 14, wherein said pixel circuits each include a liquid-crystalelement connected between a common electrode and a pixel node connectedto said data line according to a state of said selection line, a firstinsulating layer and a liquid-crystal layer having said liquid-crystalelement formed therein are deposited between a first metalinterconnection layer having said data line provided therein and a layerhaving said common electrode formed therein, a second insulating layeris present between a second metal interconnection layer having saidselection line provided therein and said first metal interconnectionlayer, said pump capacitor includes a first electrode and a secondelectrode provided in said first metal interconnection layer, a firstdummy electrode formed in the layer in which said common electrode isformed in such a manner that said first dummy electrode is opposite toboth of said first electrode and said second electrode with saidliquid-crystal layer and said first insulating layer therebetween, asecond dummy electrode formed in said second metal interconnection layerin such a manner that said second dummy electrode is opposite to saidfirst electrode with said second insulating layer therebetween, aninsulating film for allowing said second dummy electrode to stay in anelectrically floating state, and a contact portion formed in a throughhole provided in said second insulating layer for electricallyconnecting said second dummy electrode and said second electrode, andsaid pump capacitor has its capacitance represented by a syntheticcapacitance between said first electrode and said second electrode. 17.The display device according to claim 12, wherein said pixel circuitseach include a current-driven type light-emitting element indicating abrightness according to a supplied current and a current-driving unitsupplying to said current-driven type light-emitting element a currentaccording to said gray-level voltage supplied from said data line.
 18. Adisplay device displaying a gray level based on display data constitutedof weighted n bits where n is an integer of at least two, comprising: aplurality of pixel circuits each having a display element indicating abrightness according to a supplied voltage to said pixel circuit; a dataline connected to said plurality of pixel circuits; and a gray-levelvoltage generation circuit for supplying to said data line a gray-levelvoltage that is an analog voltage according to said display data, saidgray-level voltage generation circuit including a pulse control unitsuccessively receiving pulses including a first transition edge changingfrom an initial level to a predetermined level and a second transitionedge returning from said predetermined level to said initial level, andoutputting said pulses or inverted pulses that are inverted versions ofsaid pulses according to a specified bit among said n bits, a pulsenumber control circuit receiving said pulses or said inverted pulsesthat are output from said pulse control unit, and transmitting, to afirst node, said pulses or said inverted pulses of a number according tosaid display data, a first charge pump circuit increasing, in a stepwisemanner, in response to each of said pulses transmitted to said firstnode, a voltage on a first output node connected to said data line, anda second charge pump circuit decreasing, in a stepwise manner, inresponse to each of said inverted pulses transmitted to said first node,a voltage on a second output node connected to said data line.
 19. Thedisplay device according to claim 18, further comprising a prechargecircuit precharging, before said gray-level voltage is generated, saiddata line to an intermediate voltage between a maximum level and aminimum level of said gray-level voltage.
 20. The display deviceaccording to claim 18, further comprising a precharge circuitprecharging, before said gray-level voltage is generated, said data lineto one of a maximum level and a minimum level of said gray-level voltageaccording to said specified bit.